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Miscellaneous ? interfaces: ?
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One ‐ wire ? (OWIRE) ? port ?
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Three ? I2S/SSI/AC97 ? ports, ? supporting ? up ? to ? 1.4 ? Mbps, ? each ? connected ? to ? audio ?
multiplexer ? (AUDMUX) ? providing ? four ? external ? ports. ?
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Five ? UART ? RS232 ? ports, ? up ? to ? 4.0 ? Mbps ? each. ? One ? supports ? 8 ‐ wire, ? the ? other ? four ?
support ? 4 ‐ wire. ?
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Two ? high ? speed ? enhanced ? CSPI ? (ECSPI) ? ports ? plus ? one ? CSPI ? port ?
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Three ? I2C ? ports, ? supporting ? 400 ? kbps. ?
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Fast ? Ethernet ? controller, ? IEEE1588 ? V1 ? compliant, ? 10/100 ? Mbps ?
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Two ? controller ? area ? network ? (FlexCAN) ? interfaces, ? 1 ? Mbps ? each ?
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Sony ? Philips ? Digital ? Interface ? (SPDIF), ? Rx ? and ? Tx ?
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Enhanced ? serial ? audio ? interface ? (ESAI), ? up ? to ? 1.4 ? Mbps ? each ? channel ?
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Key ? pad ? port ? (KPP) ?
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Two ? pulse ‐ width ? modulators ? (PWM) ?
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GPIO ? with ? interrupt ? capabilities ?
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Secure ? JTAG ? controller ? (SJC) ?
The ? system ? supports ? efficient ? and ? smart ? power ? control ? and ? clocking: ?
? Supporting ? DVFS ? (Dynamic ? Voltage ? and ? Frequency ? Scaling) ? and ? DPTC ? (Dynamic ? Process ? and ?
Temperature ? Compensation) ? techniques ? for ? low ? power ? modes. ?
? Power ? gating ? SRPG ? (State ? Retention ? Power ? Gating) ? for ? ARM ? core ? and ? Neon ?
? Support ? for ? various ? levels ? of ? system ? power ? modes. ?
? Flexible ? clock ? gating ? control ? scheme ?
? On ‐ chip ? temperature ? monitor ?
? On ‐ chip ? oscillator ? amplifier ? supporting ? 32.768 ? kHZ ? external ? crystal ?
? On ‐ chip ? LDO ? voltage ? regulators ? for ? PLLs ?
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Security ? functions ? are ? enabled ? and ? accelerated ? by ? the ? following ? hardware: ?
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ARM ? TrustZone ? including ? the ? TZ ? architecture ? (separation ? of ? interrupts, ? memory ? mapping, ? and ? so ?
on) ?
Secure ? JTAG ? controller ? (SJC) ? – ? Protecting ? JTAC ? from ? debug ? port ? attacks ? by ? regulating ? or ? blocking ?
the ? access ? to ? the ? system ? debug ? features. ?
Secure ? real ‐ time ? clock ? (SRTC) ? – ? Tamper ? resistant ? RTC ? with ? dedicated ? power ? domain ? and ?
mechanism ? to ? detect ? voltage ? and ? clock ? glitches. ?
Real ‐ time ? integrity ? checker, ? version ? 3 ? (RTICv3) ? – ? RTIC ? type ? 1, ? enhanced ? with ? SHA ‐ 256 ? engine ?
SAHARAv4 ? Lite ? – ? Cryptographic ? accelerator ? that ? includes ? true ? random ? number ? generator ? (TRNG) ?
Security ? controller, ? version ? 2 ? (SCCv2) ? – ? Improved ? SCC ? with ? AES ? engine, ? secure/nonsecure ? RAM ?
and ? support ? for ? multiple ? keys ? as ? well ? as ? TZ/non ‐ TZ ? separation. ?
Central ? Security ? Unit ? (CSU) ? – ? Enhancement ? for ? the ? IIM ? (IC ? Identification ? Module). ? CSU ? is ?
configured ? during ? boot ? and ? by ? e ‐ fuses ? and ? determines ? the ? security ? level ? operation ? mode ? as ? well ?
as ? the ? TrustZone ? (TZ) ? policy. ?
Advanced ? High ? Assurance ? BOOT ? (A ‐ HAB) ? – ? HAB ? with ? the ? next ? embedded ? enhancements: ???????
SHA ‐ 256, ? 2046 ‐ bit ? RSA ? key, ? version ? control ? mechanism, ? warm ? boot, ? CSU ? and ? TZ ? initialization. ?
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Freescale Semiconductor
Hardware User Guide for i.MX53 Quick Start Board,
Preliminary Rev 0.91
6
PUBI – Public Use Business Information ?
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